1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a micro structure of a wiring layer and a method of forming the same.
2. Description of the Prior Art
A refractory or high-melting-point metal wiring is required in recent semiconductor devices due to the process requirements. In order to satisfy such needs, polycrystalline silicon has been used for a wiring layer. However, a metal-silicon alloy is recently used because it has a smaller resistivity than that of polycrystalline silicon. The small resistivity can improve electrical characteristics of the wiring layer. The metal-silicon alloy in this specification includes a metal silicide and a metal-silicon eutectic alloy. The metal silicides include a eutectic alloy of a metal and a metal silicide, and a eutectic alloy of a metal silicide and silicon. Typical metal silicides are MoSi.sub.x, WSi.sub.x, TiSi.sub.x, and the like. A typical metal-silicon eutectic alloy is a eutectic alloy of Al-Si.
A wiring layer of a metal-silicon alloy has a disadvantage of a large thermal expansion rate. For example, the thermal expansion rate of the metal silicide corresponds to a coefficient of linear expansion of 10 ppm/K or more. This coefficient of linear expansion is greatly larger than that (0.5 to 0.6 ppm/K) of the SiO.sub.2 film serving as the underlayer of the wiring layer. For this reason, when a heat cycle test in the temperature range of room temperature to 900.degree. C. or higher is performed, thermal stress generated between the metal silicide wiring layer and the SiO.sub.2 underlayer is 10.sup.10 dyne/cm.sup.2 or more. As a result, the thermal stress is concentrated in a step portion of the underlayer and this portion is subjected to an electrical disconnection, peeling, or cracks. The same phenomenon as described above occurs in the metal-silicon eutectic alloy.
A metal-silicon alloy wiring layer is rarely used as a single layer. A two-layered structure is employed wherein a polycrystalline silicon layer is formed between the SiO.sub.2 underlayer and the metal-silicon alloy wiring layer due to the following reasons. First, polycrystalline silicon has a thermal expansion rate as an intermediate value between the thermal expansion rates of the upper and lower layers sandwiching the polycrystalline silicon layer, and the thermal stress can be reduced by interposed polycrystalline silicon. Second, even if the metal-silicon alloy wiring layer as the upper layer is electrically disconnected by the thermal stress, the wiring function can be maintained by the polycrsytalline silicon layer formed under the metal-silicon layer. As a result, crucial failure which hinders the functioning of the device, can be avoided.
Micropatterning of elements has been developed and a wiring layer width is reduced to 1 .mu.m or less. It becomes apparent that the two-layered structure cannot satisfactorily compensate for the disadvantages of the metal-silicon alloy. In a micropatterned metal-silicon alloy wiring layer, disconnections frequently occur due to the above reason. Even if the wiring function can be maintained by the underlying polycrystalline silicon layer, a wiring resistance is undesirably increased. Therefore, it is very important to increase the strength of the metal-silicon wiring layer and to prevent electrical disconnections.
An increase in metal-silicon alloy wiring disconnections by micropatterning may be caused by a decrease in grain boundaries in the wiring layer and concentration of the thermal stress in the reduced grain boundaries. In fact, in a metal-silicide wiring, when the wiring width is decreased to 1 .mu.m or less, only one or two grains are present in the widthwise direction. Therefore, the grain boundaries of the metal silicide cross the wiring layer.
It is known to those skilled in the art that the mechanical strength of a metal silicide can be improved by adding Si thereto because excess silicon is precipitated in the grain boundaries, the grain size becomes smaller and the grain boundaries are increased. The stress acting on the grain boundaries can be uniformly distributed to the entire layer. However, this method cannot be employed to eliminate the above drawback due to the following reasons. First, in order to reduce the stress acting on the metal silicide wiring to 10.sup.10 dyne/cm.sup.2 or less according to this method, the content of the silicon component must be three times that of the metal component, and the resistivity is greatly increased. Second, the eutectic point of metal silicide-silicon is as low as 1,230.degree. C. or less. In general, the grain boundaries of the eutectic crystal are activated at a temperature corresponding to 60 to 70% of the eutectic point, i.e., 850.degree. to 1,000.degree. C., and atomic transfer occurs. The wiring of the metal-silicide silicon eutectic alloy is subjected to annealing by heating in the temperature cycle test, and the grain boundaries are changed or disappear. Therefore, the properties of the wiring layer may be degraded.